1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for detecting dishing in a polished layer.
2. Description of the Related Art
Chemical mechanical polishing (CMP) is a widely used means of planarizing silicon dioxide as well as other types of layers on semiconductor wafers. Chemical mechanical polishing typically utilizes an abrasive slurry disbursed in an alkaline or acidic solution to planarize the surface of the wafer through a combination of mechanical and chemical action. Generally, a chemical mechanical polishing tool includes a polishing device positioned above a rotatable circular platen or table on which a polishing pad is mounted. The polishing device may include one or more rotating carrier heads to which wafers may be secured, typically through the use of vacuum pressure. In use, the platen may be rotated and an abrasive slurry may be disbursed onto the polishing pad. Once the slurry has been applied to the polishing pad, a downward force may be applied to each rotating carrier head to press the attached wafer against the polishing pad. As the wafer is pressed against the polishing pad, the surface of the wafer is mechanically and chemically polished.
As semiconductor devices are scaled down, the importance of chemical mechanical polishing to the fabrication process increases. In particular, it becomes increasingly important to control and minimize within-wafer topography variations. For example, in one embodiment, to minimize spatial variations in downstream photolithography and etch processes, it is necessary for the oxide thickness of a wafer to be as uniform as possible (i.e., it is desirable for the surface of the wafer to be as planar as possible).
Those skilled in the art will appreciate that a variety of factors may contribute to producing variations across the post-polish surface of a wafer. For example, variations in the surface of the wafer may be attributed to drift of the chemical mechanical polishing device. Typically, a chemical mechanical polishing device is optimized for a particular process, but because of chemical and mechanical changes to the polishing pad during polishing, degradation of process consumables, and other processing factors, the chemical mechanical polishing process may drift from its optimized state.
FIG. 1A illustrates a cross-section of an exemplary semiconductor device 100 that is subjected to a planarization process. The semiconductor device 100 includes a substrate 110 with a plurality of trenches 120 defined therein. The trenches 120 may be used to form shallow trench isolation (STI) structures between active regions of subsequently formed devices (e.g., transistors). A silicon nitride stop layer 130 is formed over the substrate 110 and patterned to define openings used to etch the trenches 120. A silicon dioxide layer 140 is formed over the silicon nitride stop layer 130 and fills the trenches 120.
As seen in FIG. 1B, the silicon dioxide layer 140 is polished to remove the portions not disposed within the trenches 120. Typically, the polishing process continues until the silicon nitride stop layer 130 is reached. Various endpoint techniques may be used for determining the end point for the polishing process. The polishing rate of the silicon nitride stop layer 130 is less than the polishing rate of the silicon dioxide layer 140, resulting in observable changes to the polishing process parameters when the silicon nitride stop layer 130 is reached. For example, electrical parameters (e.g., motor current) of the polishing tool may be monitored to determine when the silicon nitride stop layer 130 is reached. Endpoint detection techniques are approximate, and some polishing may continue after the silicon nitride stop layer 130.
The chemical slurry used in the polishing process has a higher etch rate for oxide than for nitride. Hence, when the silicon nitride stop layer 130 is reached, the silicon dioxide layer 140 will be removed at a faster relative rate. A flexible polishing pad used in the polishing process may conform to the surface of the silicon nitride stop layer 130 and the silicon dioxide layer 140 and continue to etch the silicon dioxide layer 140 at a faster rate, resulting in a phenomenon commonly referred to as xe2x80x9cdishing.xe2x80x9d The susceptibility of the silicon dioxide layer 140 to dishing is dependent somewhat on the width and spacing (i.e., pitch) of the trenches 120. Wider features allow the polishing pad to conform to the surface easier and exacerbate a dishing problem.
Dishing may also occur during the polishing of other process layers on the semiconductor device 100. For example, interconnections are commonly formed by, depositing a conductive material (e.g., tungsten or copper) in trenches defined in an insulting layer (i.e., silicon dioxide). The conductive material is polished to remove portions not disposed in the trenches, similar to the STI process described above.
Dishing can cause various problems in the fabrication of the semiconductor device 100. For example, dishing reduces the amount of the process layer (e.g., silicon dioxide or conductive material) disposed in the trenches. If the amount of material removed is significant, the electrical properties of the features may be altered. For example, an STI structure may have reduced insulating capacity and a conductive feature may have increased resistivity. These defects can result in a reduction in the performance of the completed device (e.g., speed rating, power consumption, leakage current, etc.).
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method for polishing wafers. The method includes providing a wafer having a grating structure including a trench and a process layer formed in the trench; illuminating at least a portion of the process layer and the grating structure with a light source; measuring light reflected from the illuminated portion of the process layer and the grating structure to generate a reflection profile; and identifying dishing in the process layer based on the reflection profile.
Another aspect of the present invention is seen in a metrology tool adapted to receive a wafer having a grating structure including a trench and a process layer formed in the trench. The metrology tool includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the process layer overlying the grating structure. The detector is adapted to measure light reflected from the illuminated portion of the grating structure and the process layer to generate a reflection profile. The data processing unit is adapted to identify dishing in the process layer based on the reflection profile.